Imparé's RISC-V Verification Model

Redefining How Verification Works

The Imparé RISC-V Reference Model offers easy integration, has been extensively tested across varied environments, and allows engineers to adapt and extend it for different design needs.

Built entirely in SystemVerilog and UVM-ready, the Imparé RISC-V Verification Model enables design and verification teams to validate processor behavior efficiently, without the complexity of cross-language integration or licensing barriers.

Download our reference model to explore how open innovation meets verification-grade precision.

Comprehensive ISA Support

The Imparé RISC-V Model supports a comprehensive set of extensions, including both open source and licensed extensions:

Extensions	Type
I	Free License
M	Free License
C	Free License
F	Paid License
D	Paid License
A	Paid License

Why IRVM

Imparé's RISC-V Model enables teams to verify faster, validate smarter, and scale seamlessly across verification environments.

Model Architectural Enhancements — Experiment with new processor ideas without vendor restrictions.

Customizable Design — Add your own instruction extensions.

Scalable & Efficient — Works across embedded and high-performance systems.

Verification-Focused — Integrates as a golden reference in UVM scoreboards.

Community-Driven — Built on open standards with long-term ecosystem support.

Key features

Native SystemVerilog Implementation

No wrappers or DPI bridges

UVM-Ready Integration

Plug directly into your scoreboard

Deterministic Execution

Step-by-step validation with instruction level abstraction

Flexible Integration

Use as a reference model or stand-alone CPU core

Self-Contained Package

Delivered as riscv_class_pkg, no external dependencies

Automatic C-Extension Decoding

Expands compressed instructions internally

Simulator Compatibility

Verified on VCS, with testing underway on Questa and Xcelium

Validated for Reliability

Stress-tested with 717 real-world test cases.

Ease of Integration

Integrating the Imparé RISC-V Model into your UVM environment is seamless, with no co-simulation bridges, no DPI wrappers, and no dependency on C/C++ libraries.

The model is built entirely in SystemVerilog, providing a native and streamlined experience for verification engineers.

Integration Steps:

Connect - Link the Imparé RISC-V Model to your UVM testbench and scoreboard for instant reference-model integration.
Compile - Build and configure the riscv_class_pkg.sv package to enable instruction decoding and execution tracking.
Compare - Run DUT simulations, capture outputs, and automatically match real-time responses against the reference model for cycle-accurate validation.

Customization Capabilities

Customization is a defining strength of Imparé's model. Engineers can modify, extend, or build entirely new instruction sets in just a few steps — without altering the core architecture.

Define new instruction types or opcodes
Extend riscv_pkg.sv with new signal definitions and structures
Create custom instruction classes inheriting from inst32
Integrate your custom logic into the fetch/decode flow

This flexibility enables the addition of AI/ML accelerators, IoT low-power extensions, or domain-specific instructions for automotive, cryptographic, or robotics workloads.

Each custom extension is simulation-ready, automatically compatible with standard RISC-V instruction encodings and validated within your existing UVM setup.

Resources

Download the latest guides to explore how to integrate and operate the Imparé RISC-V Verification Model in your UVM testbench.

User Guide

Overview, usage structure, and model operation

Download now

Integration Manual

Setup, interfaces, and UVM integration examples