Webinar

RISC-V: Ready for Prime time?

Session 2: Verification Challenges of Integrating RISC-V Cores

RISC-V, the open standard instruction set architecture, is making waves in the semiconductor industry, offering customizability and efficiency. However, integrating RISC-V cores into diverse computing environments is no small feat.

This session delves into the complexities of RISC-V core integration and offers strategies to conquer the unique verification challenges faced by design and verification engineers.

AGENDA

Introduction to RISC-V: Understanding the modularity and appeal of RISC-V.
Core Integration Challenges: Exploring the intricacies of integrating RISC-V cores into SoCs, ASICs, and FPGAs.
Verification Strategies: Unveiling the tools and methodologies to address power, performance, concurrency, inter-core communication, synchronization, security, and safety concerns.
Real-World Examples: Learning from practical case studies to navigate RISC-V core integration successfully.
Q&A Session: An opportunity to get your questions answered by our experts.

Join us for an insightful exploration of the intricacies of integrating RISC-V cores and discover strategies to overcome the unique verification challenges. Whether you're an engineer or a tech enthusiast, this session will equip you with practical knowledge to succeed in the world of RISC-V integration.

Our Speakers

Saad Waheed

Senior Verification Engineer - 10x Engineers

With 4+ years in RISC-V core design verification, Saad was instrumental in verifying SiFive's U74 RISC-V high-performance Linux-capable core at Lampró Méllon. He led a team in a verification and coverage project for diverse cores during the SiFive Core IP 21G1 release. Currently, he's a senior design verification engineer at 10x Engineers, where he recently integrated the open-source RISC-V processor CVA6 into a System-on-Chip. Saad offers invaluable insights into RISC-V core verification intricacies.

Musawir Hussain

Associate Verification Engineer - Imparé

Musawir Hussain boasts expertise in RISC-V processor verification and has contributed significantly to the verification of the RISC-V Debug Module in Open Titan. As an associate verification engineer at Imparé he continues to work on cutting-edge verification challenges in the field. Musawir's experience in RISC-V and his contributions to Open Titan make him a valuable resource for understanding the intricacies of RISC-V verification.

Our Moderator

Faisal Haque

Founder and CEO - Imparé

Faisal Haque, founder of Imparé, boasts 30+ years of experience at tech giants like Intel, Cisco, and Qualcomm. He co-chaired the SystemVerilog sub-committee, authored three design and verification books, and contributed to over 10 high-profile products, including the record-breaking Cisco CRS-1 router. Faisals leadership and expertise drive Imparé's success, evident in 15+ chip tape-outs and numerous industry articles.