Senior Verification Engineer - 10x Engineers
With 4+ years in RISC-V core design verification, Saad was instrumental in verifying SiFive's U74 RISC-V high-performance Linux-capable core at Lampró Méllon. He led a team in a verification and coverage project for diverse cores during the SiFive Core IP 21G1 release. Currently, he's a senior design verification engineer at 10x Engineers, where he recently integrated the open-source RISC-V processor CVA6 into a System-on-Chip. Saad offers invaluable insights into RISC-V core verification intricacies.