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Chip Design Verification

The Tenets of Chip Design Verification

June 15, 2023

2-min read

Written by Faisal Haque, Founder & CEO of Imparé

After 25 years of working on chip design verification, some principles of verification have become obvious to me. These tenets have evolved over time through the process of learning from my many mistakes. Not everyone may agree with these rules, but I have found them to be very useful.

  1. No design is bug-free, no matter what level of verification you have done. Of course, I am not talking about two-bit adders, but rather large complex designs like an SoC, or a processor. Verification is now about minimizing the risk of critical bugs.

  2. If your tests are no longer finding bugs, change something. It can be as simple as the simulator version or as major as a new testbench. But you will be surprised how often changing something in the environment reveals a new bug.

  3. Verification mostly involves debugging code and it is hard to debug code you don’t understand. An example, I was debugging a test case which was using a pre-defined library component that was returning a null value, after spending 2 days on it, I rewrote the same code in SystemVerilog and the test case is now working. In this case, it is the same function just implemented by me. It took me 15 minutes to code, compile and test it.

  4. Do not reuse the same testbench from one generation of the design to the next. To me that is just running regressions, you are not doing verification and certainly will have a harder time finding new bugs, especially in the new features. See point no.2

  5. Over automation is not good. It stops learning and generally makes life harder for the verification engineer. See point no.3